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ICs for TV
AN5295NK
3-ch. sound signal processing single chip IC for TV (with I2C bus)
s Overview
The AN5295NK is a television-use 3-ch. sound signal processing IC which incorporates volume, tone control (L/R/C 3-ch.), and surround sound, sound AGC, lower sound enforce (L/R 2-ch.) functions. All of the functions (including changeover switch) including external I/ O port can be controlled by I2C bus.
1 30
Unit: mm
0.50.1 0.90.25
15 8.60.3 16 4.70.25 1.00.25 3.30.25 10.160.25 3 to 15
0.35-0.05
+0.1
26.70.3
s Features
* 3-ch. of volumes can be controlled independently (max. attenuation is 75 dB or more) * Center output can be switched, ether center input or inside L+R signal (for HDTV) * Lower sound enforce effect (frequency and gain) can be adjusted with external parts * With L+R output
SDIP030-P-0400
s Applications
* Television
s Block Diagram
VREF 17 Extension I/O (H/L) DAC1 7 PS GND SDA SCV SRV SCL STB SLV STT VCC LB
29
15
14
12
13
16
25
23
L-In 30
Buffer
I2C
Off On
I2C L+S L+R L-R PS LPF 1st amp.1 stage R-S C-sel Loop Add Tone Vol. Buffer 11 R-Out Add Vol.+mute 19 L-Out Tone Vol. Buffer
VCA
R-In
1
Buffer
Off
L+R
VCA
On
B-Out/ 28 C-In
Buffer
Level sense Control Bass add
On Off
22
2
6
8
LT
Tone
Vol. Buffer
18
C-Out
0 dB adj.
27
26
24
10
21
ADD
RB
CB
AGC Adj.
LS1
LS2
B-In
B-Gain
CT
RT
20
3
4
5
9
1.778
1
AN5295NK
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description R-ch. input pin Ground pin AGC 0 dB adjustment pin AGC level sensor-1 pin AGC level sensor-2 pin 1/2 VCC pin Phase shift pin L/R/C-ch. bass DAC output pin R-ch. bass fC setting pin R-ch. treble fC setting pin R-ch. output pin R-ch. volume DAC output pin L-ch. volume DAC output pin I2C communication clock pin I2C communication data pin Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Description
ICs for TV
C-ch. volume DAC output pin Extension DAC pin 1 C-ch. output pin L-ch. output pin C-ch. treble fC setting pin C-ch. bass fC setting pin L-ch. treble fC setting pin L-ch. bass fC setting pin Bass mix. gain adjustment pin L/R/C-ch. treble DAC output pin Bass detection LPF ope.-amp. input pin L+R add after AGC output pin C-ch. input pin Power supply pin (12 V) L-ch. input pin
s Absolute Maximum Ratings
Parameter Supply voltage Supply current Power dissipation
*2 *1
Symbol VCC ICC PD Topr Tstg
Rating 13.5 80 1 143 -20 to +75 -55 to +150
Unit V mA mW C C
Operating ambient temperature Storage temperature
*1
Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: Ta = 70 C.
s Recommended Operating Range
Parameter Supply voltage Symbol VCC Range 10.8 to 13.2 Unit V
2
ICs for TV
s Electrical Characteristics at Ta = 25C
Parameter Tone control Volume max. level * Volume typ. level
* *
AN5295NK
Symbol
Conditions
Min -2.3 9.2 -11.7 9.7
Typ - 0.3 11.2 -9.7 11.7
Max
Unit
VVO (max) VIN = 1 V[rms], f = 1 kHz VVO (typ) VIN = 1 V[rms], f = 1 kHz VVO (min) VIN = 1 V[rms], f = 1 kHz VBB VBC VTB VTC VIN = 400 mV[rms], f = 50 Hz VIN = 400 mV[rms], f = 50 Hz VIN = 400 mV[rms], f = 20 kHz VIN = 400 mV[rms], f = 20 kHz VIN = 1 mV[rms], f = 1 kHz VIN = 50 mV[rms], f = 1 kHz VIN = 1 V[rms], f = 1 kHz VIN = 0 mV VIN = 1 V[rms], f = 1 kHz VIN = 1 V[rms], f = 1 kHz
1.7 -75 13.2 -7.7 13.7 -8.1
dB dB dB dB dB dB dB
-16.2 -13.2 -10.2
Volume min. level Bass: boost level Bass: cut level Treble: boost level Treble: cut level AGC
-12.1 -10.1
Input/output level 1 * Input/output level 2 Input/output level 3 Circuit current
* * * *
VAGC1 VAGC2 VAGC3 ICC THD
0.7 70 275 25 2.8 12.4 2.9 4.9 3.95 -1.5 -2.0
1.7 110 345 45 0.1 115 45 14.4 4.9 6.9 5.95 -70 0 0
2.7
mV[rms]
150 mV[rms] 415 mV[rms] 65 0.5 -80 mA % V[rms] dB
Total harmonics distortion Max. input voltage Mute level
* *
VIN (max) THD = 1% VMUTE
* *
Noise level at volume max. Noise level at volume min. Surround level (max.) Surround level (min.)
* * *
VNO (max) VIN = 0 mV, Rg = 0 VNO (min) VIN = 0 mV, Rg = 0 VSU (max) VIN = 100 mV[rms], f = 1 kHz VSU (min) VIN = 100 mV[rms], f = 1 kHz VLPSUL VIN = 100 mV[rms], f = 1 kHz VBAONL VIN = 400 mV[rms], f = 50 Hz CT VIN = 1 V[rms], f = 1 kHz VIN = 1 V[rms], f = 1 kHz VIN = 1 V[rms], f = 1 kHz Maximum value of pin 15 sink current at ACK
200 V[rms] 100 V[rms] 16.4 6.9 8.9 7.95 -68.5 1.5 2.0 5.0 0.9 100 dB dB dB dB dB dB dB
Surround level at loop on Level at bass add on Cross talk
* * *
Channel balance
CB
*
L-R volume tracking (1/4) I2C interface
VTR IACK VIHI VILO fImax
Sink current at ACK SCL, SDA signal high-level input SCL, SDA signal low-level input Max. allowable input frequency
Note) * : Uses DIN audio filter.
2.0 3.5 0
10
mA V V kbit/s
3
AN5295NK
s Electrical Characteristics at Ta = 25C (continued)
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
ICs for TV
Parameter I2C interface
Symbol
Conditions
Min
Typ
Max 1.0 0.35 3.5
Unit s s s s s s s s s s s s
Bus free before start Start condition setup time Start condition hold time Low period SCL, SDA High period SCL Rise time SCL, SDA Fall time SCL, SDA Data setup time (write) Data hold time (write) Acknowledge setup time Acknowledge hold time Stop condition setup time DAC 6-bit DAC DNLE
Start condition Slave address
tBUS tSU. STA tHD. STA tLO tHI tr tf tSU. DAT tHD. DAT tSU. ACK tHD. ACK tSU. STO 1 LSB = (data (max.) - data (00))/63
ACK Sub address ACK
4.0 4.0 4.0 4.0 4.0 0.25 0 0 4.0
L6
0.1
Data byte
1.0
1.9
LSB/step
Stop ACK condition
SDA tBUF
tSU. DAT
tHD. DAT
tSU. STO
tLO
SCL tSU. STA tHDSTA
tr
tf
tHI
tLO
s Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit Description R-In: R-ch. Input pin
1 200 50 k 1/2 VCC
Voltage (V) 6
2
GND: GND pin
0
4
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 3 96 k 20 k 40 k 20 k 3 Equivalent circuit Description AGC Adj.: AGC on/off changeover AGC off at 1.2 V or less.
AN5295NK
Voltage (V)
4
18 k 900
LS1: AGC level sensor 1
250
7
4
1/2 VCC
5 Level 2 Level 1
CTL
LS2: AGC level sensor 1, 2
0.5 to 1.5
430
20 k 5
6
50 k 6 50 k
VREF : Reference voltage to be stabilized
6
7 200 18 k 8 18 k
PS: Phase shift pin 7
6
STB: L/R/C-ch. bass DAC output pin
31
8 500 3V
500 20.5 k
5.8 k
20.5 k
5
AN5295NK
s Terminal Equivalent Circuits (continued)
Pin No. 9 Equivalent circuit Description RB: R-ch. bass fC setting pin
4 k 9
ICs for TV
Voltage (V) 6
10
RT: R-ch. treble fC setting pin
6
4 k
10
11 11
R-Out: R-ch. output pin
6
12
500 500 3V 20.5 k
SRV: R-ch. volume DAC output pin
12 5.8 k 20.5 k
31
13
SLV: L-ch. volume DAC output pin
31
13 500 3V
14
500 20.5 k
5.8 k 20.5 k
SCL: I2C bus clock input pin
100 k 14 1 k 500 2.5 V
VCC
6
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 15
100 k 15 1 k 500 2.5 V
AN5295NK
Equivalent circuit
Description SDA: I2C bus data input pin
Voltage (V) VCC
16
500 500 3V 20.5 k
SCV: C-ch. volume DAC output pin
16 5.8 k 20.5 k
31
17 100 k 5.7 V 18 50 k 850 50 k
DAC1: Extension DAC output pin 17
0 or 5
C-Out: C-ch. output pin 18
6
19 19
L-Out: L-ch. output pin
6
20
CT: C-ch. treble fC setting pin
4 k 20
6
7
AN5295NK
s Terminal Equivalent Circuits (continued)
Pin No. 21 Equivalent circuit Description CB: C-ch. bass fC setting pin
ICs for TV
Voltage (V) 6
4 k
21
22
LT: L-ch. treble fC setting pin
6
4 k
22
23
LB: L-ch. bass fC setting pin
6
4 k
23
24
B-Gain: Bass mix. gain adjustment pin
6
4.7 k
24
25
STT: L/R/C-ch. treble DAC output pin
31
25 500 3V
26
500 20.5 k
5.8 k
20.5 k
B-In: Bass detection LPF ope.-amp. input pin
6
26
8
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 27 27 Equivalent circuit Description ADD: L+R (after AGC) output pin
AN5295NK
Voltage (V) 6
28
C-In: C-ch. input pin
28 200 50 k 1/2 VCC
6
29 30
200 50 k
VCC : Power supply pin L-In: L-ch. input pin
12 6
30
1/2 VCC
s Technical Information
* I2C bus 1. DAC 1) Built-in 5 DAC controls and 8 switches 2) Incorporating auto-increment functions (1) Sub address 0* : Auto-increment mode (Data are inputted by the change of sub-address according to the transfer when data are sequentially transferred.) (2) Sub address 8* : Data renewal mode (Data are inputted with the same sub-address when data are sequentially transferred.) 3) I2C bus protocol (1) Slave address: 10000000 (80H) (2) Format (normal)
S Slave address A Sub address Start condition Acknowledge bit
A
Data byte
AP Stop condition
(3) Auto-increment mode/data renewal mode S Slave address A Sub address A Data 1 A Data 2 A Data n AP
4) Typical data should be inputted at power on because initial state of DAC is not guaranteed.
9
AN5295NK
s Technical Information (continued)
* I2C bus (continued) 2. I2C bus transfer sequence
SDA
ICs for TV
SCL Start condition Slave address Acknowledge Sub address Acknowledge bit bit 00000010 0 2 Data Acknowledge Stop bit condition
10000000 8 0
00010010 1 2
Transfer message example
Two type of transfer messages of SCL and SDA are sent by synchronous serial transfer. SCL is a clock of constant frequency and SDA indicates address data to control receiving side and is sent in parallel by synchronizing with SCL. Data are transferred in principle with 8-bit 3 octet (byte) and acknowledge bit exists every one octet. Frame organization are described as follows: 1) Start condition When SDA becomes low from high at SCA = high, receiver is on a data receiving mode. 2) Stop condition When SDA becomes high from low at SCA = high, receiver stops receiving data. 3) Slave address 4) Sub address 5) Data 6) Acknowledge bit Address determined by device. Receiving is stopped when address of another device is sent. Address determined by function Data to control To let the master acknowledge that data has been received for each octet in such manner
that the master sends a high signal and the receiver sends back a low signal as shown by above transfer sequence. SDA is not changed when SCL is high except start and stop conditions. 3. Sub address byte and data byte format Upper MSB Sub address D7 00 01 02 03 04 05 0 L/R/C treble 0 0 0 0 Surround loop on/off 0 0 Data byte D6 D5 D4 D3 D2 D1 Mute on/off D0 AGC on/off
L-ch. vol. R-ch. vol. C-ch. vol.
C-ch. mute Surround on/off on/off Bass mix. on/off L/R/C bass 0 0 0 DAC1 L/H C-In select
Surround effect
10
ICs for TV
s Technical Information (continued)
* I2C bus (continued) 3. Sub address byte and data byte format (continued) 1) L-ch. Vol., R-ch. Vol., C-ch. Vol. Min. at data = 00 Max. at data = 3F 2) L/R/C treble, L/R/C bass Min. at data = 0 Max. at data = F 3) Surround effect Min. at data = 0 Max. at data = F 4) Switches (except C-ch. mute SW) Off at data = 0 On at data = 1 5) DAC1 Low (0 V) at data = 0 High (5 V) at data = 1 6) C-In select L+R in at data = 0 C-In at data = 1 7) C-ch. mute Off at data = 0 On at data = 1
AN5295NK
s Application Circuit Example
GND VREF SCV SRV STB SLV VCC 12 V STT LB 23
0.22 F
PS
17 Extension I/O (H/L) DAC1 0.1 F 7
100 F
29
15
14
12
13
16
25
L-In
10 F
30
Buffer
I2C
Off On
I2C L+S L+R L-R PS LPF 1st amp.1 stage R-S C-sel Loop Add Tone Vol. Buffer 11 R-Out
10 F
Add
VCA
Vol.+mute 19 L-Out Tone Vol. 10 F Buffer
R-In
10 F
1
Buffer
Off
L+R
VCA
On
Level sense Control B-Out/ C-In 28 Buffer
10 F
22
2
6
8
0.01 F
100 F
SDA
4.7 F
4.7 F
4.7 F
4.7 F
4.7 F
SCL
LT
Bass add
On Off
Tone
10 21
Vol. Buffer
20
18 C-Out
10 F
0 dB adj.
ADD 27 B-In 26 24 3 4 5
220 k
0.01F
0.22 F
10 F
To sound discrimination
LS1
LS2
0.015 F
100 k 10 F
12 V
RB
RT
CB
0.22F
4.7 F
0.01F
10 k
AGC Adj.
24 k
4.7 k
9
C-In: At HV Without no AGC. Possible also for 3D at 2-ch.. ADD: Add signal after AGC
C
B-Gain
Tone : LB : L-ch. bass fC LT : L-ch. treble fC RB: R-ch. bass fC RT : R-ch. treble fC CB: C-ch. bass fC CT : C-ch. treble fC
CT
11

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